The IBM Power4 Microprocessor
The IBM POWER4 is a newer microprocessor that was designed for hi-end servers and supercomputers, which are 32-way symmetric multiprocessor systems (SMP systems). The POWER4 not only refers to the actual chip but also to the structure used to interconnect chips to form systems. The POWER4 has a high fault-tolerance; when a critical fail occurs the system doesn’t just hang instead, interrupts are generated and then processed by the system. Earlier IBM Power and Power PC processors were subdivided into chips for servers (POWER) and scientific machines (RS64), however the POWER4 has been designed to efficiently run on commercial servers and scientific and technical machines. This paper will give a brief review of past POWER chips, outline the microarchitecture of the processor, and describe the interconnection architecture that is used to form 32-SMP systems. POWER4 was designed to address both commercial and technical requirements. It implements and extends in a compatible manner the 64-bit PowerPC Architecture. First used in pSeries systems, it will be staged into the iSeries at a later date. It leverages IBM technology using an 0.18-µm-lithography copper and silicon-on-insulator (SOI) technology. In the ong
• Load reorder queue (LRQ) entry: An LRQ entry must be available for each load instruction in the group. These entries are released when the group completes. The LRQ contains 32 entries. Instructions are fetched from the instruction cache (I-cache) at the address stored in the instruction-fetch address register (IFAR). The IFAR usually holds the address obtained from the branch-prediction mechanisms. Once the I-cache is accessed up to eight instructions per cycle are fetched. A line in the I-cache holds up to 32 instructions and each line is divided into four parts.
Some topics in this essay:
L2 L3,
IDIR I-cache,
PowerPC Architecture,
Issue Queues,
Austin Texas,
Cache Power4,
MHz Model,
IBM POWER4,
Multiple MCMs,
POWER4 IBM,
l3 cache,
power4 processor,
data cache,
l2 cache,
execution units,
instruction cache,
execution unit,
l1 data,
l1 data cache,
article written,
power4 microprocessor,
vol 46 no1,
46 no1 2002,
server austin texas,
ibm server austin,
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Approximate Word count = 5619
Approximate Pages = 22 (250 words per page double spaced)
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