1. The objectives of this lab were to construct flip-flop circuits and understand their fundamental properties, add another capability to our test circuitry, examine and understand the fundamental properties of the 7473 dual JK F-F, the 7474 (positive-edge triggered D-type F-F) and the 7475 (latch), to design a state machine, and to construct and analyze a synchronizer and an asynchronous counter.

• Pinouts for 7473,7474,7475 (in black binder at lab stations)

• Engineering data sheet for 555 (in black binder at lab stations)

We constructed an R-S F-F with two cross-coupled NAND gates. We used the DIP switches of our test circuitry for the R and S inputs. We monitored inputs with our logic state indicator (LED circuit) and the outputs with our logic probe.

We tested the R-S F-F under all possible combinations of input data and from this construct

In this section, we were to design a three-state machine (output of 00, 01, 10, then back to 00) using clocked F-Fs and combinational gates.

Some topics in this essay:
Analysis Conclusion, Conclusion TTL, R-S F-F, Synchronizer Procedure, JK FF, D-type F-F, J1K1 J0K0, Q1` Q0, Flip-Flops Objectives, Circuit Procedure, 555 timer, q1 q1` q0, duty cycle, analysis conclusion, q1 q1`, clock signal, 0 1, shown below, input signal, q1` q0, = 0693, table shown below, values ra rb, binder lab stations, black binder lab,