The Power3 processor brought together the fundamental design of the Power2 microarchitecture, as currently implemented on the P2SC processor, with the PowerPC Architecture. It combined the excellent floating-point performance delivered by P2SC's two floating-point execution units, while being a 64-bit, SMP-enabled processor ultimately capable of running at much higher clock speeds than current P2SC processors. Initially introduced in the fall of 1998 at a processor clock frequency of 200 MHz, most recent versions of this microprocessor incorporate copper technology and operate at 450 MHz. .
Now we come to the Power4 processor the latest design in the evolution process. The Power4 processor chip contains two microprocessor cores, chip and system pervasive functions, core interface logic, a 1.14 MB level-2 (L2) cache and controls, the level-3 (L3) cache directory and controls, and the fabric controller that controls the flow of information and control data between the L2 and L3 and between chips.
Each microprocessor contains a 64 KB level-1 instruction cache, a 32 KB level-1 data cache, two fixed-point execution units, two floating-point execution units, two load/store execution units, one branch execution unit, and one execution unit to perform logical operations on the condition. Instructions dispatched in program order in groups are issued out of program order to the execution units, with a bias towards oldest operations, and are always terminated by a branch instruction. The processor on the first IBM Power4 equipped servers, the IBM pSeries 690 Model 681 servers, operates at either 1100 MHz or 1300 MHz. We get into more detail of the components and actual design of the chip in the following section of this paper.
Power4 Chip Design.
The design of the POWER4 features two processors on one chip. The components of this chip are shown in Figure 1. .
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The components in the above chip design are:.