The IBM POWER4 is a newer microprocessor that was designed for hi-end servers and supercomputers, which are 32-way symmetric multiprocessor systems (SMP systems). The POWER4 not only refers to the actual chip but also to the structure used to interconnect chips to form systems. The POWER4 has a high fault-tolerance; when a critical fail occurs the system doesn't just hang instead, interrupts are generated and then processed by the system. Earlier IBM Power and Power PC processors were subdivided into chips for servers (POWER) and scientific machines (RS64), however the POWER4 has been designed to efficiently run on commercial servers and scientific and technical machines. This paper will give a brief review of past POWER chips, outline the microarchitecture of the processor, and describe the interconnection architecture that is used to form 32-SMP systems.
POWER4 was designed to address both commercial and technical requirements. It implements and extends in a compatible manner the 64-bit PowerPC Architecture. First used in pSeries systems, it will be staged into the iSeries at a later date. It leverages IBM technology using an 0.18- µm-lithography copper and silicon-on-insulator (SOI) technology. In the ongoing debate between the "speed demons- (high clock rate) and the "braniacs- (more complex design but a higher instructions-per-cycle rate), IBM UNIX-based systems have traditionally been in the braniac camp. With the POWER4, IBM opted to also embrace the speed-demon approach. The POWER4 design was initially introduced at processor frequencies of 1.1 GHz and 1.3 GHz, surpassing all other 64-bit microprocessors in some key performance benchmarks. .
The following are the principles that guided the design team through the designing of the POWER4 microprocessor: .
• SMP optimization: The system must be optimized for SMP, in which a large number of transistors can be used to improve total system performance.