.
• Full-system design approach: For an optimal system they began with the full design in mind; the process technology, microarchitecture, software, memory, I/O bridges and even the subsystem to feed it efficiently. .
• Very-high-frequency design: They wanted to design the chip to run at high frequencies keeping them the leaders and, design a system that would run faster as technology improved .
• Leadership in reliability, availability, and serviceability (RAS): Servers have evolved toward continuous operation. The POWER4, using not only reliable parts, can maintain a continuous system by using techniques such as ECC, error-correction-code, and others that allows the system to go around problems if possible. .
• Balanced technical and commercial performance: They wanted to design the system so that it could handle a wide variety of workloads since e-business is always evolving so the demands on the machine are always growing and changing. .
• Binary compatibility: Since there is no technical reason to change the old conventions of the PowerPC Architecture, they kept the requirements of maintaining binary compatibility for 32 and 64 bit applications for prior PowerPC systems. .
Evolution of the Power4.
.
The pSeries processors and the RS/6000 processors have went through many stages of development starting with the Power1 architecture to the latest the Power4. The Power1 was the first RS/6000 product and it was first introduced in February 1990. The first models of this RISC machine included an 8 KB instruction cache (I-cache) and either a 32 KB or 64 KB data cache (D-cache). They had a single floating-point unit capable of issuing one compound floating-point multiply/add (FMA) operation each cycle, with a latency of only two cycles. Therefore, the peak MFLOPS rate was equal to twice the MHz rate.
