For example, the Model 530 was a desk-side workstation operating at 25 MHz, with a peak performance of 50 MFLOPS. .
Two years later in January of 1992 the Model 220 was released. This machine was called a RSC machine (RISC Single Chip) since it implemented the Power Architecture on a single chip. It was designed as a low-cost desktop computer that had only a single 8 KB combined instruction and data cache. A year later the Model 580 was released. This model ran at 62.5 MHz and had a 32 KB I-cache and a 64 KB D-cache. This model was the last Power1 machine released. .
In September of 1993 the first Power2 machines were released, among these were the 55 MHz Model 58H, the 66.5 MHz Model 590, and the 71.5 MHz 990. The Power2 had enhanced the floating-point unit so that it could contain two 64-bit execution units. This meant that two floating-point multiply/add instructions could be executed each cycle, unlike the Power1 which was capable of only one instruction. The Power2 was also introduced with several new hardware instructions:.
• Quad-word storage instructions. The quad-word load instruction moves two adjacent double-precision values into two adjacent floating-point registers.
• Hardware square root instruction.
• Floating-point to integer conversion instruction.
Even thought the clock speed of the Model 590 was only slightly faster than the later Power1-based machines, it performed at much higher levels due to the combination of the above hardware instructions and a larger 256KB D-cache.
Three years later in 1996, IBM announced the first machines to be based on the P2SC processor (Power2 Super Chip). The P2SC was a single chip implementation of the Power2 architecture which allowed for a greater clock speed. First was the Model 595 which ran at 135 MHz, and later came the Model 397 and RS/6000 SP which ran at 160 MHz. The Model 397 and RS/6000 SP were the last and fastest models to implement the Power2 architecture through the P2SC chips.
